New opportunity

Senior/Staff Deep Learning Compiler Engineer

quadric · India

About this role

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. As a Senior/Staff Deep Learning Compiler Engineer, you will design and optimize the compiler stack connecting ML frameworks directly to Quadric's GPNPU architecture, driving graph optimizations, memory efficiency, and hardware co-design to unlock peak performance for edge AI workloads.

Responsibilities

Design, implement, and maintain compiler optimization passes targeting Quadric’s processor architecture using frameworks like MLIR, Apache TVM, or LLVM.
Develop lowering pathways from high-level machine learning frameworks (PyTorch, TensorFlow, ONNX) down to optimized low-level kernel code.
Optimize neural network performance for memory throughput, latency, compute unit utilization, and power consumption.
Implement graph-level optimizations, including operator fusion, layout transformation, quantization (INT8/FP16), and memory allocation strategies.
Analyze novel deep learning model topologies (Transformers, CNNs, Vision-Language Models) and extend compiler support for new operators and primitives.
Benchmark and profile end-to-end model performance to identify and resolve compiler bottlenecks.
Collaborate closely with hardware and micro-architecture teams to define instruction set extensions, hardware acceleration features, and compiler requirements.
Develop software simulators, functional models, and test benches to validate compiler correctness and generated binary performance.
Participate in hardware bring-up and validation efforts on FPGA and ASIC platforms.

Required qualifications

8 years+ experience alongwith BS, MS, or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
Hands-on experience developing deep learning compilers or compiler infrastructures (e.g., MLIR, Apache TVM, LLVM, XLA, TensorRT, or Glow).
Strong proficiency in C++ (14/17/20) and Python, with solid fundamentals in data structures, algorithms, and object-oriented design.
Familiarity with modern AI/ML frameworks (PyTorch, TensorFlow, ONNX) and deep learning operator representations.
Solid understanding of computer systems, memory hierarchies, parallel processing, and CPU/GPU/NPU instruction execution.

Preferred qualifications

Experience with low-level kernel optimization, SIMD/vector programming, and memory allocation strategy development.
Knowledge of model quantization methodologies (INT8, FP8, mixed-precision) and post-training/QAT optimization techniques.
Prior experience working on software stacks for custom AI accelerators, DSPs, or embedded architectures.
Experience with FPGA bring-up, hardware emulation, or cycle-accurate simulator development.

Benefits

Medical, dental, and vision insurance
Equity with the business
Paid Parental Leave
PF Retirement Plan
Flexible PTO
Winter holiday shutdown
Catered lunch each day in our office
Downtown Pune office location, close to shops, cafes, and local amenities
Collaborative, low-ego culture with significant ownership and impact
A work culture focused on innovative disruption

For full details about this role, click “Apply on company site” to view the employer’s original posting.

Skills for this role

MLIRTVMLLVMC++PythonPyTorchTensorFlowONNX

Checking your profile…

Preparation suggestions, not the employer’s actual interview questions. Always check the original posting for current requirements.

Understand the role

What matters most

Compiler Infrastructure and Optimization Passes
Design, implement, and maintain compiler optimization passes targeting Quadric’s proprietary GPNPU processor architecture using robust frameworks like MLIR, Apache TVM, or LLVM.
Framework Lowering Pathways and Graph Transformations
Develop seamless lowering pathways from high-level machine learning frameworks such as PyTorch, TensorFlow, and ONNX down to optimized low-level kernel code, incorporating operator fusion, layout transformation, and quantization strategies.
Hardware-Software Co-Design and Benchmarking
Collaborate closely with hardware and micro-architecture teams to define instruction set extensions and compiler requirements while benchmarking end-to-end model performance across simulators and physical platforms.

Likely challenges to think through

Bridging High-Level Frameworks with Novel GPNPU Architecture
A core difficulty lies in mapping flexible, high-level graph representations from frameworks like PyTorch or ONNX onto Quadric's unique General-Purpose Neural Processing Unit architecture without incurring high runtime overhead. To prepare, study intermediate representation (IR) lowering techniques in MLIR or TVM and practice designing custom codegen optimization passes for non-traditional compute topologies.
Balancing Memory Throughput and Low-Power Constraints at the Edge
Edge AI workloads demand extreme efficiency in memory bandwidth, latency, and power consumption, which can conflict with heavy model topologies like Transformers or Vision-Language Models. Preparation should focus on mastering memory allocation strategies, operator fusion, and quantization methodologies such as INT8 and FP16 to optimize constrained hardware targets.
Aligning Software Stack Development with Hardware Bring-Up
Co-designing software stacks concurrently with FPGA and ASIC bring-up introduces risks of shifting hardware specifications and debugging elusive binary-level discrepancies. Candidates should review hardware simulation methodologies, functional modeling, and techniques for validating compiler correctness against cycle-accurate or virtual targets.

Practice your answers

Technical practice

Designing Custom Compiler Optimization Passes

What to coverDiscuss how you would design and implement a custom optimization pass in MLIR, Apache TVM, or LLVM targeting a specialized processor architecture. Focus on intermediate representation (IR) traversal, pattern matching, and preserving correctness during graph transformations.

Lowering High-Level Framework Graphs

What to coverExplain the process of lowering high-level neural network operations from PyTorch, TensorFlow, or ONNX down to low-level target kernel code. Address handling dynamic shapes, custom operators, and bridging high-level semantic graphs to hardware primitives.

Operator Fusion and Memory Bandwidth Optimization

What to coverExplain how operator fusion minimizes memory round-trips and improves memory throughput for edge AI workloads. Discuss trade-offs when fusing compute-bound versus memory-bound operations under strict power and buffer constraints.

Model Quantization Strategies (INT8 and FP16)

What to coverDescribe the compiler and runtime challenges involved in implementing quantization strategies such as INT8 and FP16. Address calibration, handling quantization error propagation, and generating efficient instructions for quantized data types.

Supporting Novel Model Topologies

What to coverHow would you analyze and extend compiler support for emerging model topologies like Vision-Language Models or complex Transformers? Address identifying computational bottlenecks, memory access patterns, and introducing new compiler primitives.

Memory Allocation and Layout Transformations

What to coverDiscuss strategies for static memory planning and buffer reuse in embedded or edge architectures. Explain how layout transformations (such as channel-last versus channel-first formatting) impact cache locality and compute unit utilization.

Hardware-Software Co-Design and Instruction Set Extensions

What to coverWhen collaborating with micro-architecture teams, how do you evaluate the need for new instruction set extensions or hardware acceleration features? Address using data-driven workload analysis and software simulators to influence hardware specs.

Benchmarking and Performance Profiling

What to coverDescribe your approach to profiling end-to-end model execution on custom hardware or software simulators to isolate compiler bottlenecks. Discuss metrics such as latency, compute unit utilization, and power consumption.

Compiler Validation and Testing Infrastructure

What to coverHow do you build robust software test benches and functional models to validate compiler correctness against generated binary performance? Address regression testing and verification across simulation and physical FPGA or ASIC platforms.

Behavioural practice

Cross-Functional Collaboration with Hardware Teams

What to coverDescribe a situation where you had to collaborate closely with hardware or micro-architecture engineers to resolve a performance or design bottleneck. Using the situation, action, and result framework, explain how you communicated software constraints and reached an agreement on hardware extensions or requirements.

Resolving Complex Performance Bottlenecks

What to coverShare an instance where an end-to-end deep learning workload failed to meet latency or memory throughput targets. Detail the profiling steps you took, how you isolated the compiler bottleneck, and the resulting optimization that solved the issue.

Handling Ambiguity in New Model Topologies

What to coverGive an example of a time when you had to rapidly understand and extend a compiler stack to support a novel model or framework primitive with sparse documentation. Outline your approach to analyzing the problem, prototyping a solution, and validating its correctness.

Balancing Technical Trade-Offs Under Tight Constraints

What to coverDiscuss a project where you had to make a difficult trade-off between compiler compilation time, runtime execution efficiency, and memory footprint. Explain how you evaluated the options, collaborated with stakeholders, and justified your final design choice.

Sharpen your knowledge

Topics to prepare

Deep Learning Compiler Infrastructure and Lowering
Study intermediate representation (IR) design, graph lowering pathways, and optimization passes in frameworks like MLIR, Apache TVM, or LLVM. Relevant because the role requires designing and maintaining optimization passes targeting Quadric's GPNPU processor architecture and bridging high-level ML frameworks to hardware.
Memory Hierarchy and Graph-Level Optimizations
Review memory allocation strategies, operator fusion, layout transformations, and quantization methods (INT8/FP16). Relevant to optimize neural network memory throughput, latency, and power consumption for edge AI workloads.
Hardware-Software Co-Design Principles
Examine how compiler requirements influence instruction set extensions, SIMD/vector programming, and custom hardware accelerators or DSPs. Relevant because the position collaborates closely with hardware teams on architecture definitions and FPGA/ASIC validation.

Skills to revise

Advanced C++ (14/17/20) and Python Programming
Practice implementing robust data structures, algorithms, and object-oriented patterns in modern C++ and Python. Relevant due to the explicit requirement for strong proficiency in both languages to build compiler infrastructure and tools.
MLIR, Apache TVM, or LLVM Development
Hands-on practice writing custom compiler passes, operator extensions, or lowering logic within MLIR, TVM, or LLVM. Relevant because hands-on experience developing deep learning compiler infrastructure is a core qualification.
AI/ML Framework Integration and Graph Profiling
Work with PyTorch, TensorFlow, and ONNX operator representations, parse model topologies, and profile end-to-end performance bottlenecks. Relevant to develop lowering pathways and extend compiler support for modern Transformers and CNNs.

Your preparation checklist

Map Experience to Deep Learning Compiler Frameworks
Compile a structured record of your hands-on work with MLIR, Apache TVM, LLVM, XLA, TensorRT, or Glow, highlighting specific optimization passes, lowering pathways, and architectural targets you have built or maintained.
Prepare a Deep Learning Compiler Project Walkthrough
Draft a detailed technical walkthrough of a complex compiler infrastructure project you led or contributed to, focusing on graph transformations, operator fusion, memory allocation strategies, or quantization techniques.
Review Modern AI Model Topologies and Frameworks
Brush up on operator representations and execution patterns for recent deep learning topologies such as Transformers, CNNs, and Vision-Language Models across frameworks like PyTorch, TensorFlow, and ONNX.
Prepare Evidence for C++ and Systems Fundamentals
Gather code examples or architectural notes demonstrating advanced C++ (14/17/20) proficiency, data structures, parallel processing concepts, memory hierarchies, and instruction execution mechanics.
Formulate Technical Questions for the Engineering Team
Prepare thoughtful questions regarding Quadric's GPNPU architecture, hardware-software co-design workflows, software simulation environments, and integration processes for FPGA or ASIC platforms.

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