About this role
Drive RTL-to-GDS synthesis and timing closure for NPU IPs and subsystems, develop and maintain synthesis flows, constraints, and automation, and optimize designs for PPA while collaborating with RTL, DFT, STA, and Physical Design teams and supporting tapeout activities.
Skills for this role
RTL SynthesisTiming ClosureConstraint DevelopmentSynopsys Design CompilerSynopsys Fusion CompilerCadence GenusPrimeTimeUPFLow-power Design MethodologiesClocking ArchitectureTiming SignoffTCLPythonPerlPhysical-aware SynthesisHierarchical Design MethodologiesLECCDCLintPower AnalysisLow-power VerificationSDCPPA OptimizationScriptingAutomationRTL-to-Gate SynthesisStatic Timing Analysis (STA)Design for Test (DFT)Physical Design CollaborationNPU