About this role
Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems, and develop and maintain synthesis flows, constraints, and automation to optimize PPA and support tapeout activities.
Skills for this role
RTL-to-gate synthesisRTL synthesisTiming closureConstraint developmentASIC design flowSynopsys Design CompilerSynopsys Fusion CompilerCadence GenusPrimeTimeLow-power design methodologiesUPFClocking architectureTiming constraintsTiming signoffTCLPythonPerlLECCDCLintPower analysisLow-power verificationPhysical-aware synthesisHierarchical design methodologiesScripting and automationSoC/IP tapeoutsAI/ML acceleratorsNPUDSPGPU