About this role
Drive RTL-to-gate synthesis and timing closure for NPU IPs and subsystems, develop and maintain synthesis flows, constraints, and automation, and collaborate with RTL, DFT, STA and Physical Design teams to meet PPA targets and support tapeout activities on advanced process nodes.
Skills for this role
RTL-to-gate synthesisTiming closureConstraint developmentSynopsys Design CompilerSynopsys Fusion CompilerCadence GenusPrimeTimeUPFLow-power design methodologiesClocking architectureTiming signoffTCLPythonPerlPhysical-aware synthesisHierarchical design methodologiesLECCDCLintPower analysisLow-power verificationSDC (timing constraints)Synthesis flow automationQuality of Results (QoR) analysisSoC/IP tapeoutsCross-functional collaborationASIC design flow (RTL to GDS)