NPU AI/Processor Synthesis Engineer- Sr Lead

Qualcomm India Private Limited seeks a Synthesis Engineer/Lead for its Neural Processing Unit (NPU) design team. The role drives RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators in next-generation SoCs, working with architecture, RTL design, STA, DFT and physical design teams to deliver power-efficient silicon.

Responsibilities

• Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems. Build and maintain synthesis flows, timing constraints and automation for complex hierarchical designs.
• Drive pre-layout and post-layout timing closure across multiple modes and process corners. Use physical-aware synthesis to optimize performance, power and area (PPA).
• Create and validate SDC constraints, clock definitions, false paths and multicycle paths. Resolve quality-of-results, timing, power and convergence issues with partner teams.
• Perform LEC, CDC, lint and low-power verification checks; improve synthesis results through scripting and flow enhancements; and support tapeouts.

Qualifications

• Minimum qualifications provide alternatives: a bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or a related field with 3+ years of hardware engineering or related experience; a master's degree in one of those fields with 2+ years; or a PhD in one of those fields with 1+ year. The posting separately lists a bachelor's or master's degree in Electrical Engineering, Electronics, Computer Engineering or a related field under required qualifications.
• Required expertise includes the ASIC flow from RTL to GDS; hands-on RTL synthesis, timing closure and constraint development; Synopsys Design Compiler or Fusion Compiler, or Cadence Genus; PrimeTime timing analysis; low-power methodologies and UPF flows; clocking architecture and timing signoff; and TCL with Python or Perl scripting. Debugging, problem-solving and cross-functional collaboration are also required.
• Preferred qualifications include work on AI/ML accelerators, NPUs, DSPs, GPUs, CPUs or other high-performance compute architectures; knowledge of 5nm, 4nm, 3nm or smaller nodes; physical-aware synthesis and hierarchical design; familiarity with LEC, CDC, lint, power analysis and low-power verification; and successful SoC or IP tapeouts.

The posting lists Bangalore and Hyderabad, India, as locations and identifies the position as full-time.