About this role
Drive RTL-to-GDS synthesis and timing closure for NPU IPs and subsystems, developing and maintaining synthesis flows, constraints, and automation. Collaborate with RTL, DFT, STA, and Physical Design teams to optimize designs for PPA, perform quality checks (LEC/CDC/lint), and support tapeout activities.
Skills for this role
RTL-to-GDS synthesisASIC design flowRTL synthesisTiming closureConstraint developmentSDC (timing constraints)Clocking architectureMulti-cycle path creationSynopsys Design CompilerFusion CompilerCadence GenusPrimeTimeLow-power design methodologiesUPF-based flowsTCLPythonPerlPhysical-aware synthesisHierarchical design methodologiesLECCDCLintPower analysisLow-power verificationPPA optimizationSTADFTPhysical DesignSoC tapeoutsIP tapeouts