The AI/ML ASIC Architect will develop advanced system architectures for Sandisk’s next-generation AI storage solutions. You will drive new architecture initiatives, leveraging frontend interfaces like UCIe to integrate AI storage solutions with xPU accelerators in 2.5D/3D package systems. Responsibilities include authoring architecture specifications, collaborating with cross-functional teams (RTL, DV, Simulation, Emulation, FW), and assessing product performance, power, area, and endurance. Key duties involve defining SoC subsystems, software/firmware interactions, and conducting LLM workload analysis to identify performance improvements. Required qualifications include a Bachelor's degree with 7+ years of experience, a Master's degree with 5+ years, or a PhD with 3+ years, including at least 2 years of ASIC experience. Candidates must possess a strong technical background in ASIC, SoC, UCIe, and architecture specification authoring, along with a deep understanding of computer/graphics architecture, LLMs, and GPU/TPU systems with optimized high-bandwidth memory hierarchies for multi-trillion parameter LLM training and inference.
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A focused preparation guide, built around this job’s responsibilities and requirements.
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01
Understand the role
What matters most
Integration of AI Storage with xPU Accelerators
The core of this role is architecting systems that bridge AI storage solutions with GPU/TPU accelerators using UCIe interfaces. You must demonstrate the ability to design 2.5D/3D package systems that optimize data flow and latency for high-performance computing environments.
LLM Workload Analysis and Characterization
You are expected to conduct deep analysis of LLM workloads to identify performance bottlenecks. This requires a strong grasp of memory hierarchies, specifically regarding high-bandwidth memory and KV cache optimizations, to inform architectural decisions that improve training and inference efficiency.
Cross-Functional Architecture Specification
You must author clear, technical architecture specifications that serve as the blueprint for RTL, DV, Simulation, Emulation, and Firmware teams. Success depends on your ability to define SoC subsystems and software/firmware interactions that align with hardware capabilities.
Likely challenges to think through
Balancing Performance, Power, Area, and Endurance
Architecting for AI storage involves conflicting trade-offs between high-speed throughput and power/thermal constraints. Prepare to discuss how you evaluate these metrics during the design phase and how you justify architectural compromises to cross-functional stakeholders.
Complexity of 2.5D/3D Packaging and UCIe
Implementing advanced packaging and UCIe interfaces introduces significant physical and logical design challenges. Prepare by reviewing the latest UCIe standards and being ready to explain how you manage signal integrity and interconnect complexity in heterogeneous integration projects.
03
Practice your answers
Technical practice
UCIe Integration in 2.5D/3D Packaging
What to coverExplain the architectural challenges of integrating AI storage solutions with xPU accelerators using UCIe. Discuss how you manage signal integrity, latency, and power distribution in 2.5D/3D package systems.
LLM Workload Analysis and Performance Optimization
What to coverDescribe your methodology for characterizing LLM workloads to identify performance bottlenecks. Focus on how you translate these findings into specific ASIC architectural improvements.
High Bandwidth Memory (HBM) Hierarchies
What to coverHow do you design memory hierarchies to support multi-trillion parameter LLM training and inference? Address the trade-offs between bandwidth, capacity, and power consumption in these systems.
KV Cache Optimization Strategies
What to coverDiscuss techniques for optimizing KV cache in the context of large-scale inference. Explain how your architectural choices impact memory footprint and latency during the generation phase.
SoC Subsystem and Firmware Interaction
What to coverExplain how you define the interaction between hardware subsystems and firmware. Provide examples of how you balance hardware-level acceleration with firmware-based control for storage management.
ASIC Architecture Specification Authoring
What to coverWhat is your process for writing clear and concise architecture specifications for cross-functional teams? Emphasize how you ensure alignment between RTL, DV, and emulation teams.
Assessing Power, Area, and Performance (PPA)
What to coverDescribe your approach to evaluating PPA trade-offs during the early stages of ASIC design. How do you prioritize these metrics when they conflict in an AI storage context?
Collaboration with Verification and Emulation
What to coverHow do you work with DV and emulation teams to validate complex architectural changes? Explain how you use simulation results to iterate on your initial design specifications.
Behavioural practice
Cross-Functional Collaboration
What to coverDescribe a situation where you had to align RTL, firmware, and verification teams on a complex architectural decision. How did you resolve conflicting technical requirements?
Driving New Architecture Initiatives
What to coverGive an example of a time you proposed and drove a new architectural initiative. What was the challenge, what actions did you take to gain buy-in, and what was the outcome?
Handling Technical Ambiguity
What to coverDescribe a project where the requirements for an AI storage solution were initially unclear. How did you define the scope and ensure the final architecture met performance goals?
Managing Trade-offs in Design
What to coverTell me about a time you had to make a difficult trade-off between performance, power, and area. How did you justify your decision to stakeholders?
02
Sharpen your knowledge
Topics to prepare
UCIe and 2.5D/3D Packaging Architectures
Review the Universal Chiplet Interconnect Express (UCIe) specification, focusing on its role in die-to-die communication within 2.5D and 3D packaging. Practice explaining how chiplet-based architectures facilitate the integration of AI storage with xPU accelerators, as this is central to the role's requirement for next-generation storage solutions.
LLM Workload Analysis and Memory Hierarchies
Study the memory access patterns of multi-trillion parameter LLMs, specifically focusing on KV cache optimization and high-bandwidth memory (HBM) requirements. Prepare to discuss how storage-side ASIC architecture can mitigate bottlenecks in training and inference workflows by optimizing data movement between storage and accelerators.
Skills to revise
ASIC Architecture Specification Authoring
Practice drafting a concise technical specification for a hypothetical SoC subsystem. Focus on clearly defining the interactions between hardware, firmware, and software, ensuring that performance, power, area, and endurance metrics are explicitly addressed as required by the role.
SoC Subsystem Definition and Integration
Develop a block diagram or architectural flow for an AI storage SoC that interfaces with an external GPU/TPU. Focus on the data path, control logic, and firmware-hardware handoff mechanisms, ensuring the design accounts for the high-throughput demands of AI/ML workloads.
04
Your preparation checklist
Analyze UCIe and 2.5D/3D Packaging Integration
Prepare a technical summary of how UCIe facilitates chiplet-based communication in 2.5D/3D systems. Be ready to discuss the trade-offs in latency, power, and bandwidth when integrating AI storage solutions with xPU accelerators.
Review LLM Workload and Memory Hierarchy Requirements
Prepare to discuss your experience with multi-trillion parameter LLM training and inference. Focus on how high-bandwidth memory hierarchies and KV cache optimizations impact ASIC performance and endurance.
Draft an Architecture Specification Walkthrough
Prepare a sample or a structured outline of an architecture specification you have authored. Highlight your ability to define SoC subsystems and the interactions between hardware, firmware, and software.
Prepare Cross-Functional Collaboration Examples
Identify specific instances where you worked with RTL, DV, Simulation, Emulation, and Firmware teams to evaluate design changes. Focus on how you assessed performance, power, area, and endurance metrics.
Formulate Strategic Questions for the Interview
Prepare questions regarding the specific AI storage challenges Sandisk is prioritizing, the current roadmap for UCIe adoption in their 2.5D/3D products, and how the architecture team balances performance with memory endurance.
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