About this role
Qualcomm India Private Limited seeks an engineer or lead for RTL design of AI/ML-related subsystems in Bangalore, India. The role works closely with product definition and architecture teams to develop microarchitecture and coding strategies that meet subsystem quality and performance, power, area and schedule (PPAS) goals.
Responsibilities
- Define block diagrams, interfaces, clocking, transaction flow, pipelines and low-power aspects of block-level designs. Perform RTL coding for subsystem and SoC integration, lead other engineers, and debug functional and performance simulations.
- Drive lint, clock-domain crossing, formal verification and UPF checks; develop assertions for white-box testing and coverage. Work with stakeholders on design-collateral quality, solutions and workarounds, and deliver timing constraints and UPF collateral.
- Define bandwidth, latency and bus-transaction sizing for use cases across voltage and frequency corners. Collaborate with power and synthesis teams on dynamic-power use cases and datapath interactions, and exchange collateral with SoC design-for-test and physical-design teams.
Desired skills include low-power microarchitecture, AI/ML system and computer architecture, high-performance design trade-offs, NoC design, Verilog or SystemVerilog, simulation and waveform-debugging tools, and logic design with an understanding of timing and power implications.
Minimum qualifications are a bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or a related field plus 3+ years of hardware engineering or related experience; a master's degree in one of those fields plus 2+ years; or a PhD in one of those fields plus 1+ year. Preferred qualifications include a bachelor's or master's degree in Electronics or Electrical Engineering or equivalent and at least 2+ years working on multiple designs.